1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a mask ROM, a method for fabricating the same and a method for coding the same. The method for forming the mask ROM maximizes integration and packing density of a device.
2. Discussion of the Related Art
Generally, a flat ROM device is made by a method for fabricating a semiconductor device. That is, the flat ROM device is so-named because its Bit-Line and Word-Line are formed at a step lower than that of other memory devices. A mask ROM is made as a desired cell that is selectively coded with ‘0’ or ‘1’ by a mask process.
A related art mask ROM and a method for fabricating the same will be described.
FIG. 1A is a sectional view illustrating a related art mask ROM viewed from a Bit-Line direction, and FIG. 1B is a sectional view illustrating a related art mask ROM viewed from a Word-Line direction.
As shown in FIG. 1A, in the related art mask ROM viewed from a Bit-Line direction, a plurality of Word-Lines comprise a polysilicon gate electrode layer 13a and a silicide layer 14a patterned at a predetermined width on a substrate 10 provided with a gate oxide film 12. An insulating film 15 is formed between the patterns.
As shown in FIG. 1B, in the related art mask ROM viewed from a Word-Line direction, a gate oxide film 12 is formed on a substrate 10 defined by buried N doped (BN) junction regions 11 formed at predetermined portions. A polysilicon layer 13 and a silicide layer 14 are sequentially formed on the gate oxide film 12. The gate oxide film 12 is relatively thicker than any other portions. The BN junction regions 11 buried on the substrate 10 serve as Bit-Lines.
The related art mask ROM is fabricated as follows.
First, a device isolation region (not shown) is formed on a semiconductor substrate 10 by a local oxidation of silicon (LOCOS) process or a shallow trench isolation (STI) process. Also, a region other than the device isolation region is defined as an active region.
After a well is formed in the active region, a nitride film (not shown) is deposited on the semiconductor substrate 10. After a photoresist pattern is coated and predetermined portions of the photoresist pattern are removed, the nitride film is patterned such that its width is the same width as the photoresist pattern. Ions are implanted into a predetermined portion on the semiconductor substrate 10 using the nitride film as a mask to define impurity ion regions. The defined impurity ion regions are BN junction regions 11.
Subsequently, after the nitride film is removed, the semiconductor substrate 10 is cleaned, and a gate oxide film 12 is formed on the semiconductor substrate 10. The gate oxide film 12 formed on the BN junction regions 11 is thicker than other portions of the gate oxide film 12.
Next, a polysilicon layer 13 is deposited on the gate oxide film 12 and then selectively removed to form a gate electrode layer 13a. 
The gate electrode layer 13a undergoes reoxidation to form a silicide layer 14a. Each structure that comprises the gate electrode layer 13a and the silicide layer 14a serves as a Word-Line.
Subsequently, regions between the structures that comprise the gate electrode layer 13a and the silicide layer 14a are filled with the insulating film 15.
Then, lightly doped drain (LDD) regions and heavily doped junction regions are formed by ion implantation.
In the process of fabricating the related art flat cell type mask ROM device, which may be a flat cell type mask ROM, the BN junction regions 11 used as Bit-Lines are formed by annealing after implanting ions into the active region.
As shown in FIG. 1B, regions between the BN junction regions 11 are channels of a cell transistor, and the BN junction regions 11 serve as source and drain regions.
The BN junction regions 11 are formed with a long depth in a flat ROM device. Resistance between lines of the BN junction regions 11 impedes driving of a cell. Therefore, each BN junction region 11 requires a proper depth and a proper line width to maintain resistance at a proper value. However, with the trend towards decreased cell sizes, it is difficult to obtain a proper depth and a proper line width due to a required channel margin.